1. Field of the Invention
The present invention relates to a memory device and a method for manufacturing the same, and more particularly, to a flash memory device having a lightly doped source and a method for manufacturing the same.
2. Description of the Related Art
A typical structure of arranging nonvolatile memory cells is disclosed in xe2x80x9cA SINGLE TRANSISTOR EPROM CELL AND ITS IMPLEMENTATION IN A 512K CMOS EEPROMxe2x80x9d, IDEM pp 616-619, 1985. FIG. 1 is a sectional view of a conventional nonvolatile Erasable and Programmable Read Only Memory (EPROM) type NOR flash memory cell. Referring to FIG. 1, a first insulating layer 330, a floating gate 340, a second insulating layer 350 and a control gate 360 are sequentially formed on a semiconductor substrate 300. Also, a drain 310 and sources 320 and 322 are formed in a predetermined region under the surface of the semiconductor substrate 300. The source comprises a highly doped region 320 and a lightly doped region 322 surrounding the highly doped region 320. The lightly doped region 322 and the highly doped region 320 are partially overlapped by the floating gate 340. Also, the drain 310 is doped with a high concentration impurity, and the drain 310 is partially overlapped by the floating gate 340. The first insulating layer 330 is formed of a tunnel oxide layer in which electrons can be tunneled.
Operation of an EPROM type NOR flash memory cell will be described below. The EPROM type NOR flash memory cell has programming, erasing and reading operations. When a high voltage is applied to a bit line connected to the drain 310 and to a word line connected to the control gate 360 to program a cell, hot electrons are generated at the drain junction. The hot electrons pass through the first insulating layer 330 and then are injected into the floating gate 340 and thus the hot electrons are stored in the floating gate 340. Accordingly, the threshold voltage of a device is increased, so that the device is programmed. The electrons stored in the floating gate 340 must be removed to erase the programmed device. When a high voltage is applied to the source, the electrons stored in the floating gate move to the source in a Fowler-Nordheim (F-N) tunneling manner to be erased from the floating gate 340.
Accordingly, the program operation of a nonvolatile memory device is performed by electron injection in the drain 310. Here, the electrons injected into the floating gate 340 are partially trapped by the first insulating layer 330. Characteristics of the first insulating layer 330 are deteriorated by the trapped electrons. Also, the erasing operation of the device is performed through the source. Here, the tunneled electrons are trapped by the first insulating layer 330 formed between the floating gate 340 and the sources 322 and 320, and thereby deteriorate the characteristics of the device.
The size of a cell is reduced to realize high-integration of a nonvolatile memory device. However, the drain 310 requires a depletion region for generating hot-carriers under the floating gate 340, so that the drain 310 and the floating gate 340 must overlap each other. Also, in order to lower the applied voltage during the erase operation, the highly doped source must partially overlap the floating gate 340 to directly tunnel the carriers. Also, in order to prevent the generation of the breakdown in the highly doped source 320 by the applied voltage during the erase operation, a lightly doped source 322 must surround the highly doped source 320. Moreover, an effective channel length between the source and the drain 310 under the floating gate 340 is required, so that the channel is capable of operating as a memory device, as well as in a region where the source and the drain 310 overlap the floating gate 340. Therefore, the integration of the nonvolatile memory device is reduced.
FIG. 2 is a sectional view of a memory cell in which a highly doped source 320 and a floating gate 340 overlap each other. Reference numeral 324 indicates a depletion region formed in a junction region of the lightly doped source 322 and the semiconductor substrate 300 when a voltage is applied to the source for the erase operation. Here, electrons stored in the floating gate 340 tunnel to the source as indicated by the arrows. Thus, in a memory cell in which the highly doped source 320 and the floating gate 340 overlap with each other, a low voltage is applied to the source to cause electron tunneling. If the highly doped source 320 does not overlap with the floating gate 340, electrons stored in the floating gate 340 tunnel through the depletion region to the highly doped source 320. Thus, in a memory cell in which the highly doped source 320 and the floating gate 340 do not overlap with each other, a high voltage must be applied to the highly doped source to cause electron tunneling. It is preferable that the highly doped source 320 and the floating gate 340 overlap with each other to lower the applied voltage during the erase operation. Thus, in a memory cell in which the electrons stored in the gate are erased in the F-N tunneling manner, each of the highly doped source 320 and drain 310 must overlap with the floating gate 340, so that it is difficult to increase the integration of the nonvolatile memory device.
An EPROM having a lightly doped source is disclosed in U.S. Pat. No. 4,652,897. The structure of a device disclosed in the U.S. Pat. No. 4,652,897 will be described with reference to FIGS. 3 and 4. Referring to FIG. 3, a first insulating layer 510, a floating gate 340, a second insulating layer 350 and a control gate 360 are sequentially stacked on a semiconductor substrate 300. Also, a drain 310, a lightly doped source 502 and a highly doped source 500 are formed around the surface of the semiconductor substrate 300. Here, the impurity concentration of the lightly doped source is 1xc3x971016xcx9c1xc3x971017 atoms/cm3, and the length W1 along the gate of FIG. 3 is 0.3xcx9c0.4 xcexcm. The drain 310 and the lightly doped source 502 are overlapped by the floating gate 340. The first insulating layer 510 is a gate oxide layer.
FIG. 4 is a graph showing the electric field intensity b1 and potential a1 in a cell during programming of a memory cell. Referring to FIG. 4, it can be shown that the electric field intensity b1 is increased in the lightly doped source 502 having a high resistance. Thus, in the memory cell of FIG. 3, hot-carriers generated in the lightly doped source 502 are then injected into the floating gate 340, to thereby program the memory cell. Also, in the memory cell of FIG. 3, an electric erase operation cannot be performed and thus the electrons stored in the floating gate 340 are erased by exposing them to ultra-violet light.
FIG. 5 is a sectional view of a memory cell in which electrons stored in the floating gate 340 can be electrically erased through a source. Referring to FIG. 5, a gate oxide layer 512 and a tunnel oxide layer 514 are formed instead of the first insulating layer 330 of FIG. 3. Thus, the program operation is the same as that of the memory cell disclosed in FIG. 3, but the erase operation is electrically performed through the source. That is, when a high voltage is applied to the highly doped source 500 in an erase operation, the electrons stored in the floating gate 340 move across the tunnel oxide layer 514 by tunneling.
However, in the memory cell disclosed in FIG. 5, the highly doped source 500 and the floating gate 340 do not overlap with each other. Thus, in order to cause tunneling of the electrons stored in the floating gate 340, a relatively high voltage must be applied to the highly doped source 500 considering the resistance and the depletion region in the lightly doped source 502, so that the memory cell has operational requirements which are difficult to meet. Also, a high electric field is applied to the lightly doped source 502 during the erase operation, so that many hot carriers are generated in the lightly doped source 502 and thus the number of traps between the tunnel oxide layer 514 and the lightly doped source 502 are increased. Thus, resistance of the memory cell is increased, so that characteristics of the memory cell are changed.
To solve the above problems, it is an objective of the present invention to provide a nonvolatile memory device in which electrons stored in a floating gate are electrically discharged to a semiconductor substrate, to thereby suppress deterioration of the characteristics of a first insulating layer due to electrons trapped in the first insulating layer, and highly doped source has a reduced depth, to thereby enhance the integration of the memory cell.
It is another objective of the present invention to provide a method for manufacturing a nonvolatile memory device.
Accordingly, to achieve the first objective, there is provided a nonvolatile memory device comprising: a semiconductor substrate of a first conductivity type; a first insulating layer, a floating gate, a second insulating layer and a control gate sequentially stacked on the semiconductor substrate; a highly doped source of a second conductivity type formed around the surface of the semiconductor substrate, spaced away from the sidewall of the floating gate; a lightly doped source of the second conductivity type formed around the surface of the semiconductor substrate, connected to the highly doped source, overlapped by the floating gate, having an impurity concentration lower than that of the highly doped source; and a drain of a second conductivity type formed around the surface of the semiconductor substrate, overlapped by the floating gate, deeper than the highly doped source, having an impurity concentration same as that of the highly doped source.
It is preferable that the lightly doped source has an impurity concentration of 5xc3x971017xcx9c5xc3x971018 atoms/cm3 and the lightly doped source has a length of 0.2 xcexcm or less in the direction of the floating gate from an edge of the highly doped source. A programming operation of the nonvolatile memory device is performed by generating hot carriers in a depletion region of the drain, when a voltage is applied to the drain and the control gate, and injecting part of the generated hot carriers into the floating gate from a region where the drain region and the floating gate overlap with each other so that the hot carriers are stored in the floating gate, and erase operation of the nonvolatile memory device is performed by tunneling the electrons stored in the floating gate by the program operation into the semiconductor substrate, when a voltage is applied to the semiconductor substrate.
Also, a nonvolatile memory device having a cell region and a peripheral circuit region formed on a semiconductor substrate of a first conductivity type, comprises: a first insulating layer, a floating gate, a second insulating layer and a control gate which are sequentially formed on the semiconductor substrate of the cell region; a highly doped source of a second conductivity type formed around the cell region surface of the semiconductor substrate, and spaced apart from the side wall of the floating gate; a lightly doped source of the second conductivity type formed around the cell region surface of the semiconductor substrate, connected to the highly doped source, overlapped by the floating gate, and having an impurity concentration lower than that of the highly doped source; a drain of a second conductivity type formed around the cell region surface of the semiconductor substrate, overlapped by the floating gate, having the same impurity concentration as that of the highly doped source; and a MOS transistor formed in the peripheral circuit region, having the structure of a lightly doped drain. Here, preferably, the impurity concentration of the lightly doped source in the cell region is higher than that of the lightly doped drain of the MOS transistor in the peripheral circuit region.
It is also preferable that the depth of the drain in the cell region is deeper than that of the highly doped source in the cell region.
To achieve the second objective, there is provided a method for manufacturing a nonvolatile memory device comprising: (a) forming a stacked gate where a first insulating layer, a floating gate, a second insulating layer and a control gate are stacked in a cell region of a semiconductor substrate having a cell region and a peripheral circuit region; (b) implanting an impurity and diffusing the impurity to form a drain overlapped by part of the stacked gate; (c) implanting an impurity with a dose lower than that of the drain to form a lightly doped source overlapped by part of the stacked gate; (d) forming a spacer on the sidewall of the stacked gate; (e) forming a photoresist layer pattern on the drain; (f) performing implantation into the lightly doped source using the stacked gate, the spacer and the photoresist layer pattern as a mask to form a highly doped source connected to the lightly doped source, without being overlapped by the stacked gate, having a depth lower than that of the drain.
Preferably, in implanting the impurity and difussing the impurity to form the drain, the implantation is performed with a dose of 2xc3x971015xcx9c6xc3x971015 ions/cm2. The implantation of an impurity with a dose lower than that of the drain to the form the lightly doped source preferably comprises forming a photoresist layer pattern exposing the source of the cell region; implanting an impurity using the photoresist layer pattern as a mask; and implanting an impurity into the entire surface of the semiconductor substrate after removing the photoresist layer pattern. Here, preferably, the implanting of an impurity using the photoresist layer pattern as a mask is performed with a dose of 3xc3x971013xcx9c6xc3x971013 ions/cm2, and the implanting of an impurity into the entire surface of the semiconductor substrate is performed with a dose of 1xc3x971013xcx9c3xc3x971013 ions/cm2. It is also preferable that a lightly doped source and drain of a MOS transistor is formed on the peripheral circuit region of the semiconductor substrate during the implanting of an impurity into the entire surface of the semiconductor substrate. Also, in the forming of the highly doped source region, the implantation is performed with a dose of 2xc3x971015xcx9c6xc3x971015 ions/cm2. Preferably, a lightly doped drain of a MOS transistor is formed on the peripheral circuit region of the semiconductor substrate during the implanting of an impurity into the entire surface of the semiconductor substrate. Also, the lightly doped source and drain of the MOS transistor in the peripheral circuit region of the semiconductor substrate are formed with an impurity concentration lower than that of the lightly doped source of the cell region. It is also preferable that the highly doped source of the cell region and the highly doped source and drain in the peripheral circuit region of the semiconductor substrate is formed to have a depth lower than that of the drain of the cell region. The nonvolatile memory device is a flash memory device.
According to the present invention, the depth of the highly doped source is reduced and the floating gate and the highly doped source are not overlapped, thereby increasing the integration of the memory cell. Also, electrons stored in the floating gate are tunneled to the semiconductor substrate during an erase operation of the memory cell, so that electron trapping in the first insulating layer formed between the lightly doped source and the floating gate can be prevented, to thereby achieve stable operation characteristics for the memory device.